Agenda
General Session
Time
Topic
Speaker
08:30 - 09:30
Registration and Welcome Breakfast / Photo Booth
09:30 - 10:00
From Point Tools to Agentic AI: How EDA has impacted the Semiconductor Industry
Don Chan, Vice President, R&D in the Digital & Signoff Group, Cadence
10:00 - 10:30
Smart Products and Solutions to Emerging Technologies
Srikanth Settikere, Vice President and Managing Director of the Microchip India Development Center
10:30 - 11:00
Morning Tea Break
Track 1: Custom IC and Mixed Signal
Studio 1 and 2
Time
Topic
Speaker
11:00 - 11:20
Reimagining Custom IC Design with AI Agents in Virtuoso® Studio
Wan-Tat Hooi, Senior Application Engineering Manager
11:20 - 11:40
Efficient Block and Chip-Level Analog/AMS Simulations and Analysis with Spectre® Technologies and AI/ML
Zhong Fan, Senior Product Engineering Group Director
11:40 - 12:00
Automated GPNR Batch Flow for Rapid Placement and Routing of Custom IP
Choong-Jin Teoh from Intel
12:00 - 14:00
Lunch at Kucina, Level 3 / SAGO, Level 2 / Level 12 / Ballroom, Level 2
14:00 - 14:30
AI‑Assisted Post‑Layout Simulation Diagnosis and Parametric What‑If Optimization
Murally Murugan from Intel
14:30 - 15:00
Testbench-Driven Migration to Reduce Runtime and Storage with Virtuoso Schematic Mapping
Ee-Peng Yeoh and Zhi-Hong Chong from Intel
15:00 - 15:30
Advanced Aging Analysis Using Dynamic Parameters for Burn-In and End-of-Life Reliability Assessment
Jing-Wen Lee and Nur Syarafina Zahari from Intel
15:30 - 16:00
Agentic AI for Circuit Synthesis and Interactive Schematic Editing in Virtuoso
Eugene Ooi and Jingwen Lee from Intel
16:00 - 16:30
Afternoon Tea Break
16:30 - 17:00
Enhancing Communication Efficiency Through Virtuoso’s Design Intent
Joel Thomas Matthew and Ruffy Ugay from Infineon
17:00 - 17:30
Wrap-Up and Lucky Draw
Track 2: System and Verification Group
La Siena
Time
Topic
Speaker
11:00 - 11:40
AI Powered Verification: A New Era of Accelerated Frontend Design
Simon Chang, Senior AE Group Director
11:40 - 12:00
End to End Agentic Verification with ChipStack™ AI Super Agent
Chen Jie, Application Engineering Director
12:00 - 14:00
Lunch at Kucina, Level 3 / SAGO, Level 2 / Level 12 / Ballroom, Level 2
14:00 - 14:30
Reducing Debugging Effort with Verisium™ Debug and AI Assistant
Rich Chang, Product Marketing Director
14:30 - 15:00
Jasper® Bound Signoff Technique - To Deliver High-Quality Formal Verification Results with Undetermined properties
Hugh Lo, Senior Principal Application Engineer
15:00 - 15:30
Flattening the Learning Curve: Boosting Productivity with Jasper AI Agents
Bill Lin, Lead Product Engineer
15:30 - 16:00
Verisium AI: Intelligent Automation for Debug, Regression, and Resource Optimization
Ngoc Nam Ho, Senior Principal Application Engineer
16:00 - 16:30
Afternoon Tea Break
16:30 - 17:00
Using Functional Cover Convergence to Estimate Required Bounded Proof Depth
Vivian Lee and Suhanya Jayaprakasam from Intel
17:00 - 17:30
Wrap-Up and Lucky Draw
Track 3: Digital Implementation and Signoff
Grand ballroom
Time
Topic
Speaker
11:00 - 12:00
AI Agents Delivering Digital Chip Design Productivity Benefits - Innovation for digital chip design
Kiran Tangirala, Senior Application Engineering Manager
12:00 - 14:00
Lunch at Kucina, Level 3 / SAGO, Level 2 / Level 12 / Ballroom, Level 2
14:00 - 14:30
From Specification to Signoff: InnoStack and the Rise of AI Super Agents
Jeff Handong, Product Engineering Group Director
14:30 - 15:00
Fanout‑Driven Reset Flop Duplication for Timing Closure in High Frequency Macro Dominant Design
Zhi-Sheng Choon and Wei-Liang Woon from SkyeChip
15:00 - 15:30
LOS Scan Enable Timing Convergence with Physical-Aware Cloning Approach
Wan-Hui See and Wei-Liang Woon from SkyeChip
15:30 - 16:00
Improving Physical Consistency Using Master/Clone Methodology in Hierarchical APR Flows
Muhammad Rifaie Bin Rodzil and Chee-Wung Ngo from SkyeChip
16:00 - 16:30
Afternoon Tea Break
16:30 - 17:00
Full chip Hybrid Implementation Flow using Innovus
Wen-Chin Lim and Hock-Ban Lim from SkyeChip
17:00 - 17:30
Wrap-Up and Lucky Draw
Track 4: System Design and Analysis
Studio 3 and 4
Time
Topic
Speaker
11:00 - 12:00
Accelerating System-Level Signoff: Recent Innovations in Sigrity™ and Clarity™ with GPU, AI, and Integrations
Jian Liu, VP Research & Development
12:00 - 14:00
Lunch at Kucina, Level 3 / SAGO, Level 2 / Level 12 / Ballroom, Level 2
14:00 - 14:30
PCIe & DDR IP Solutions for the AI Era and ARM® CSS Validation
Eric Li, Senior AE Manager
14:00 - 14:30
Introducing Allegro® X Integrated Layout Editor in System Capture
Chin-Pin Khwang, Senior Principal Application Engineer
15:00 - 15:30
Allegro X AI: Enabling Parallel, AI-Driven PCB Design for Faster and Optimized System Development
Adam Fuchs, Senior Principal Product Engineer
15:30 - 16:00
Shift-Left Multi-Physics Analysis with Sigrity Aurora: From In-Design Screening to System-Level Signoff
Yongxin Fang, Senior Principal Application Engineer
16:00 - 16:30
Afternoon Tea Break
16:30 - 17:00
Accelerating Hardware Development Through Hierarchical Common Building Blocks
Jason Wong from Celestica
17:00 - 17:30
Wrap-Up and Lucky Draw
*Notice: Agenda is subject to change.