Track 1: Custom IC and Mixed Signal

Reimagining Custom IC Design with AI Agents in Virtuoso Studio by Wan-Tat Hooi, Senior Application Engineering Manager

 Custom IC design becoming more complex and time consuming. AI powered Virtuoso Studio helps designers work more efficiently by bringing intelligent assistance into familiar design flows. It helps automate repetitive tasks, provides helpful guidance during design and verification, and reduces trial and error. Instead of replacing designers, AI agent supports their work by offering suggestions and insights at the right time. This makes it easier to complete designs faster, improve quality, and handle challenging analog and mixed signal designs with greater confidence. In this session, we will unlock latest AI features in Virtuoso Studio and how designer can prepare themselves with AI agent in custom design world

Efficient Block and Chip-Level Analog/AMS Simulations and Analysis with SpectreX/FX, AMS Designer and StatsAI by Zhong Fan, Senior Product Engineering Group Director

 As the industry’s leading solution for accurate analog simulation, the Cadence Spectre Simulation Platform provides a comprehensive portfolio of custom simulation solutions for analog and mixed-signal design and verification teams. The platform contains multiple solvers that serve as the computational foundation and allow a designer to move easily and seamlessly between circuit-, block-, and system-level simulation tasks. The solvers are integrated with a wide range of complementary technologies to provide the industry’s most complete solution for custom verification problems. In addition, Spectre FMC (Fast Monte Carlo) Analysis enables fast and comprehensive design space exploration using Monte Carlo simulations of complex analog, RF, I/O, mixed-signal blocks, memories, standard cells, and bit cells while maintaining necessary statistical accuracy. It works with the Spectre X and Spectre APS Simulators and allows you to distribute Monte Carlo simulation workloads to increase throughput.

Enhancing Communication Efficiency Through Virtuoso’s Design Intent by Thomas Matthew from Infineon

 Throughout the project lifecycle layout engineers must translate circuit designers’ requirements into a physical implementation while meeting a wide range of electrical, physical, and manufacturing constraints, including device placement, matching, and routing rules. Effective communication between circuit designers and layout engineers is therefore essential, yet often challenging, especially when teams are distributed across different time zones. This presentation introduces Virtuoso’s Design Intent as a structured and efficient communication mechanism that provides a graphical interface allowing designers to embed intent directly within both the schematic and layout environments. This approach enables clear visualization of critical constraints and instructions within the appropriate design context. In traditional workflows, schematic constraints and layout instructions are often shared through emails or messaging apps, leading to fragmented or inconsistent information, misinterpreted requirements, inefficient handoffs or ownership transfers, and longer turnaround times. Beyond one-way annotation, the system enables true bidirectional communication, creating an interactive feedback loop that resolves issues earlier, minimizes iteration cycles, and strengthens collaboration between design and layout teams. Additionally, Virtuoso’s Design Intent automatically generates a final HTML handshake report that consolidates all instructions and communication history. This ensures full traceability, improves documentation quality, and supports a more efficient and reliable IC layout workflow.

AI‑Assisted Post‑Layout Simulation Diagnosis and Parametric What‑If Optimization by Lucan Tan and Jing-Wen Lee from Intel

 This work presents an automated diagnosis and What If analysis solution for Analog post layout simulation, addressing the common scenario where pre layout results meet specification but post layout verification fails. The system connects directly to the Cadence simulation environment and automates this debug process. Rather than manually inspecting simulation logs and tracing signal paths through complex design files, the tool connects directly to the simulation environment, detects which checks have failed, and investigates the cause automatically. The solution supports interactive correction especially on failures occur because a signal is being measured at the wrong location — a mismatch introduced when the physical layout is generated. The tool identifies such mismatches by comparing where a signal is expected against where it actually appears in the physical design and proposes a correction. Beyond connectivity repair, the system enables automated What If sweeps on design parameters. Rather than the designer manually deciding what to change and re-running simulations by hand, the tool identifies and tests design adjustments automatically, iterating until the target performance is met. This integrated flow streamlines root cause analysis, accelerates post layout debug, and provides a foundation for intelligent design space exploration in advanced Analog verification.

Testbench-Driven Migration to Reduce Runtime and Storage with Virtuoso Schematic Mapping by Ee-Peng Yeoh and Zhi-Hong Chong from Intel

 Many migration programs tightly control schematic scope, but testbench migration is often executed in bulk, which can carry forward inactive legacy content and unnecessary dependencies. This presentation describes a testbench-driven migration methodology implemented with the Cadence Virtuoso Analog Schematic Migration tool, using a predefined set of schematic top cells as the starting point. From these top cells, the method identifies the relevant active testbenches, computes the complete schematic dependency closure required to support them, and executes migration in a single batch with consistent mapping rules. This replaces a common two-step sequence in which schematics are migrated in a scoped pass and testbenches are migrated later in a separate, broader pass, increasing reruns and storage growth due to nonessential legacy artifacts. In deployment, the methodology reduced runtime and disk usage by approximately 89% each and reduced filesystem inode consumption by approximately 73%.

Advanced Aging Analysis Using Dynamic Parameters for Burn-In and End-of-Life Reliability Assessment by Jing-Wen Lee and Nur Syarafina Zahari from Intel

 As semiconductor devices continue to scale, accurate prediction of aging effects becomes critical for ensuring product reliability throughout the device lifetime. This presentation explores enhanced dynamic parameter capabilities for comprehensive burn-in and end-of-life (EOL) aging analysis. The dynamic parameter feature enables designers to model gradual aging effects and accelerated burn-in processes used in high-volume manufacturing (HVM) for early defect detection. This capability is particularly valuable for IP characterization, allowing design teams to estimate aging drift and implement effective mitigation strategies before tape-out. Recent enhancements include improved stimulus generation for accelerated and different aging scenarios. These improvements enable accurate prediction of cumulative aging effects from both burn-in stress conditions and operational lifetime degradation. We demonstrate practical workflows for integrating aging analysis into existing design verification flows, showcasing how dynamic parameters can model time-dependent parameter shifts in transistors and interconnects. Results show significant improvement in aging drift estimation accuracy, enabling proactive design guardbanding and reliability optimization for advanced technology nodes.

Interactive Schematic Editing with Agentic AI in Virtuoso by Eugene Ooi and Jingwen Lee from Intel

 Schematic editing is a manual, time-intensive process. It requires designers to execute repetitive tasks, such as placing symbols, routing wires, and assigning properties, while also requires deep circuit expertise and tool familiarity. Although SKILL scripting offers partial automation, it introduces development and maintenance overhead. To elevate this workflow, this paper presents an Agentic AI framework built directly into the Virtuoso Schematic Editor, offering a seamless experience through Virtuoso UI integration. The framework interprets high-level design intent via natural language and autonomously executes schematic tasks, such as component placement and pin connection, without requiring manual canvas interaction or custom SKILL code. Going beyond simple automation, the framework also incorporates advanced topology understanding and hierarchical awareness to interpret high-level design intent via natural language. Ultimately, this scalable solution significantly reduces schematic editing time, minimizes human error, and frees designers to focus on higher-level architectural decisions.

Automated GPNR Batch Flow for Rapid Placement and Routing of Custom IP from Choong-Jin Teoh and Wei-Jian Teh from Intel

 Migrating custom mixed-signal IP to advanced process nodes while preserving functionality and electrical performance is a growing VLSI challenge. This presentation describes an automated physical design placement and routing flow implemented with Cadence Gigaplace and Nanoroute to accelerate the layout construction. The flow executes in batch mode to automate floorplan generation, constraint propagation, and placement/routing of custom digital blocks which utilizing standard cells, delivering a streamlined workflow to reduce placement and routing time and manual effort during layout integration.