Track 2: System and Verification Group

AI Powered Verification: A New Era of Accelerated Frontend Design by Simon Chang, Senior AE Group Director
Chip verification is at an inflection point, as rising design complexity and compressed schedules demand a new approach to frontend design and verification. This presentation outlines a forward looking view of how AI is transforming frontend design into a catalyst for faster, higher quality verification by embedding intelligence early to reduce debug effort, coverage closure time, and integration rework. At the core of this approach is system co validation enabled by the “Dynamic Duo” of emulation and prototyping, which brings hardware and software together early to validate real system behavior and enable true shift left execution. The session also highlights AI optimized formal verification with Jasper to accelerate proof convergence, the use of verification IP to rapidly cover complex interfaces, timing aware verification to address constraints at the RTL stage, and integrated power analysis to align functionality, performance, and energy efficiency from the outset. Together, these capabilities redefine verification as a continuous, intelligent accelerator for first silicon success.

End to End Agentic Verification with ChipStack™ AI Super Agent by Chen Jie, Application Engineering Director
Chip verification remains one of the most time and resource intensive phases of SoC development, with teams relying on fragmented automation and heavy manual iteration. The ChipStack™ AI Super Agent introduces an end to end agentic verification workflow that drives verification tasks directly from specifications and RTL. By orchestrating specialized agents for test planning, testbench generation, simulation and formal execution, coverage analysis, and debug, ChipStack targets step function productivity gains while keeping engineers in control of review and sign off. At the core of the Super Agent is the mental model, which is a unified, evolving representation of design intent extracted from specs, RTL, and other design artefacts. This mental model serves as the single source of truth that enables cross agent reasoning, consistent iteration, and goal driven verification closure. This session will explain how ChipStack AI Super Agent transforms verification from script based automation into a coherent, autonomous workflow, and how teams can deploy it seamlessly alongside existing Cadence tools to accelerate coverage closure and time to market.

Reducing Debugging Effort with Verisium Debug and AI Assistant by Rich Chang, Product Marketing Director
Verisium Debug, Cadence's unified debug platform, has evolved with the integration of AI technology. Debugging continues to be a resource-intensive component of the verification process, often requiring engineers to possess in-depth knowledge of both design principles and tool functionality. The addition of the Verisium Debug AI Assistant allows users to utilize natural language commands to operate the platform, streamlining data generation for design analysis and delivering precise information for bug tracing. Engineers no longer need to consult manuals to identify features; by simply asking questions in natural language, the Verisium Debug AI Assistant facilitates efficient and effective debugging. This presentation will outline the latest capabilities of the Verisium Debug AI Assistant and provide a live demonstration to illustrate how Verisium Debug AI can significantly reduce debugging workloads.

Jasper Bound Signoff Technique - To deliver high quality formal verification results with undetermined properties from Hugh Lo, Senior Principal Application Engineer

 Based on Jasper’s comprehensive coverage analysis and powerful bound-pushing capabilities, the proposed Bound Signoff methodology and flow can deliver high-quality verification results even in the presence of undetermined properties, which are common in high complexity designs. In essence, it provides an alternative from the traditional “expertise + time” (achieving full property convergence) to scalable “compute resources + job arrangement” (pushing properties to higher bounds with confidence). As real project schedules continue to tighten, this represents a practical and increasingly important advancement.

Flattening the Learning Curve: Boosting Productivity with Jasper AI Agents from Bill Lin, Lead Product Engineer

 As AI reshapes the semiconductor industry, Cadence is driving a structured evolution toward more intelligent workflows. In this session, we’ll start with a high-level roadmap of Cadence’s AI offerings, moving from basic optimization to fully autonomous systems. We will showcase how the Jasper AI portfolio aligns with this broader vision to transform formal verification. We will briefly talk about how AI agents are democratizing advanced formal technologies: Tasks that used to require a formal expert, such as managing proof structures or applying SST onto hard-to-converge property are now accessible to new users through natural language chat boxes. By lowering these barriers, we’re opening up advanced verification techniques to a larger user base. We will dive deep into the Visualize Agent, which solves two major bottlenecks. First, it flattens the learning curve and makes powerful features available to all users. Second, it revolutionizes the time-consuming and tedious counterexample debugging process by providing initial hints and guidance which junior engineers typically lack. Integrating these AI agents into your daily work can truly be a time-saver and game changer.

Verisium AI: Intelligent Automation for Debug, Regression, and Resource Optimization by Ngoc Nam Ho, Senior Principal Application Engineer

As chip complexity continues to grow, verification teams face mounting pressure to reduce turnaround time, minimize manual effort, and extract actionable insights from massive regression datasets. This presentation introduces Verisium AI — Cadence's intelligent, action-oriented AI layer built on the JedAI Platform — designed to transform how engineers operate and optimize the Verisium verification environment. The Verisium AI Assistant (vM Assistant) enables engineers to query live verification data and documentation using natural language, instantly delivering root cause analysis, session statistics, and actionable recommendations without manual investigation. Beyond the assistant, three AI-powered flows are available in the Early Adopter release (v25.09.020): Debug Ready — enabling parallel, automated failure clustering and root cause.

Using Functional Cover Convergence to Estimate Required Bounded Proof Depth by Vivian Lee from Intel

 In bounded formal verification, determining an appropriate proof depth is a practical challenge. Insufficient depth may leave deep corner-case behaviors unexplored, while excessive depth increases runtime and computational cost without proportional confidence gain. A structured method for estimating required bounded proof depth can be derived from functional cover convergence. The approach defines functional cover properties that capture meaningful architectural behaviors, including long-latency operations, pipeline interactions, feedback paths, and rare state transitions. By observing the maximum bound required to hit all functional covers, a measurable indicator of the deepest explored reachable behavior is obtained. Safety properties can then be proven to at least this maximum cover depth, aligning proof effort with demonstrated state-space exploration. Although this technique does not replace formal completeness thresholds or full inductive proofs, it provides a practical and defensible confidence metric in bounded analysis. The method integrates naturally with assertion-based verification flows and coverage reporting mechanisms, offering a systematic way to justify depth targets. Correlating cover convergence with bounded proof depth improves convergence efficiency and strengthens confidence that significant reachable behaviors have been thoroughly analyzed within the explored bounds.