Track 3: Digital Implementation and Signoff

AI Agents Delivering Digital Chip Design Productivity Benefits - Innovation for digital chip design by Kiran Tangirala, Senior Application Engineering Manager

 Advances in artificial intelligence are transforming digital chip design by enabling higher productivity, faster convergence, and scalable automation across implementation and signoff. This presentation introduces Cadence’s vision for AI driven digital design, highlighting the evolution from optimization centric AI to fully agentic workflows and emerging autonomy. Built on the Cadence® JedAI platform, these innovations integrate models, data, reasoning, and compute to deliver intelligent assistance throughout the RTL to GDSII flow. We showcase AI assistants and agents embedded in core tools such as Stratus™, Innovus+™ AI, Tempus™, and Pegasus™, spanning AI driven RTL generation from specification, intelligent digital implementation, and AI enabled signoff. Agentic workflows monitor, analyze, and correct design health issues by combining deterministic analytics with LLM based reasoning, enabling faster root cause analysis and prescriptive fixes. Accumulated and contextual learning across multiple runs further accelerates PPA convergence without additional compute. The presentation also highlights practical agent deployments, including power grid generation from high level specifications, automated timing path analysis, log and constraint intelligence, and knowledge assistants that provide instant, context aware expertise. Together, these AI agents redefine digital implementation and signoff, reducing manual effort, shortening turnaround time, and enabling teams to focus on higher value design decisions.

From Specification to Signoff: InnoStack and the Rise of AI Super Agents by Jeff Handong, Product Engineering Group Director

 Providing an overview of the Cadence Agentic AI framework, this presentation highlights the structure of tool agents and super agents with a focus on InnoStack: tool agents offer a natural language interface that enables users to issue high-level commands for debugging, health checks, and analysis, significantly reducing the need for detailed tool command knowledge; the framework supports both interactive and auto modes, where interactive mode facilitates real-time debugging and direct user interaction, while auto mode allows agents to analyze databases in the background, delivering self-healing capabilities or prompting users for input when issues cannot be resolved automatically; additionally, InnoStack provides robust session management by supporting multiple concurrent sessions, allowing users to work on several designs simultaneously and seamlessly switch between them within the same UI while maintaining clear context separation.

Fanout‑Driven Reset Flop Duplication for Timing Closure in High Frequency Macro Dominant Design from Zhi-Sheng Choon and Wei-Liang Woon from SkyeChip

 In high frequency physically constrained designs, a single reset source register may drive multiple destination flops distributed across the floorplan, leading to long datapaths and excessive buffer insertion which will cause timing violations. This presentation proposes an implementation driven methodology in Cadence Innovus to duplicate selected high fanout reset source flops along with their associated combinational logic and place them at user defined locations closer to respective load clusters. Targeted load reassignment is subsequently performed to ensure each destination flop is driven by the nearest duplicated source, thereby reducing datapath delay. As this approach introduces intentional logic replication, instance level constraints are incorporated to enable successful Logical Equivalence Checking (LEC) using Cadence Conformal, ensuring logical equivalence between the original and implementation netlists.

LOS Scan Enable Timing Convergence with Physical-Aware Cloning Approach from Wan-Hui See and Wei-Liang Woon from SkyeChip

 The requirement is to meet one functional clock cycle for scan_enable path at atspeed mode and it becomes a challenge when the given netlist only consists of one set of pipeline scan flop logic and existing high fanout synthesis flow introduced longer logic depth during optimization. This presentation shows an alternative approach to minimize the logic depth of the paths, through cloning the group of pipeline scan flop logics using Innovus tool. The effort had shown to be able to reduce logic depth and resolve timing for one functional clock cycle as the cloned instances are distributed nearer to their fanouts.

Improving Physical Consistency Using Master/Clone Methodology in Hierarchical APR Flows by Muhammad Rifaie Bin Rodzil from SkyeChip

 Driven by advanced process nodes and faster design targets, maintaining physical consistency across repeated logic structures within a single APR partition becomes challenging, particularly when cloneable and non-cloneable architectures coexist. For this case, a partition must remain integrated due to a mix of symmetrical and non-symmetrical logic, preventing straightforward top-level replication while still containing internally repeated structures that require matching with replicated neighbouring partitions. Variations in layout can lead to differences in parasitic resistance and capacitance, affecting timing predictability. This presentation introduces a methodology that leverages Hierarchical Flow Capabilities in Cadence’s Innovus automated placement and routing, utilizing a Master/Clone approach. A reference instance is first implemented and then replicated across equivalent structures, enabling the maintenance of physical characteristics across all instantiated designs. This approach improves RC consistency and timing uniformity across replicated structures while minimizing repetitive manual effort, helping preserve interface timing, data path alignment, and clock skew consistency. By combining automated replication with structured partitioning strategies, design teams can enhance productivity and achieve predictable timing, thereby accelerating overall design turnaround.

Full chip Hybrid Implementation Flow using Innovus by Wen-Chin Lim and Hock-Ban Lim from SkyeChip

 Modern SoC designs continue to grow in complexity, requiring scalable and efficient methodologies to achieve predictable implementation quality and faster turnaround time. This work presents a hybrid full chip design planning and implementation flow that integrates top down architectural planning with bottom up hierarchical development. The methodology emphasizes early floorplanning, intelligent pin assignment, and systematic feedthrough planning for both clock and data paths to minimize timing risks and routing congestion. A topology file based approach is introduced to guide clock distribution in multi instantiated blocks, ensuring balanced latency and consistent architecture reuse. Additionally, a structured repeater lookup table generation flow enables optimized buffering decisions across long distance interconnects, reducing iterations, and improving electrical performance. The hierarchical implementation framework supports parallel block development, accelerating runtime while preserving global connectivity intent. Early post assembly verification further provides rapid QoR insights before full signoff. Together, these techniques deliver a robust and scalable solution for full chip planning and implementation in advanced SoC designs.