Track 4: System Design and Analysis

Accelerating System-Level Signoff: Recent Innovations in Sigrity and Clarity with GPU, AI, and Integrations By Jian Liu, VP Research & Development
As advanced packaging, 3D-IC, high-speed interfaces, and AI infrastructure continue to push design complexity, system-level signal integrity, power integrity, and electromagnetic analysis require new levels of capacity, accuracy, and automation. This talk will highlight recent innovations in Cadence Sigrity and Clarity that address these challenges through high-performance GPU acceleration, AI-assisted workflows, and deeper integration across the design and analysis ecosystem. We will discuss how GPU-enabled electromagnetic and power integrity engines are improving simulation throughput for large-scale packages, boards, and interconnect structures, while maintaining the accuracy required for signoff-quality results. The presentation will also introduce emerging AI capabilities that help streamline setup, improve modeling productivity, guide analysis decisions, and accelerate convergence from design intent to actionable results. In addition, we will cover advances in integrated workflows connecting Sigrity, Clarity, packaging, PCB, and system analysis environments, enabling engineers to move more efficiently from layout to extraction, simulation, optimization, and signoff. Through recent customer-driven examples and technology updates, attendees will gain insight into how Cadence is advancing scalable, intelligent, and integrated analysis solutions for next-generation electronic systems

Introducing Allegro X Integrated Layout Editor in System Capture by Chin-Pin Khwang, Senior Principal Application Engineer
A new layout environment within Allegro X System Capture platform – offers a cutting-edge solution for layout design. The interoperability between Allegro X System Capture and Allegro layout editor ensures compatibility and easy transition of layout designs. The user interface of Allegro X Layout Editor is designed to be intuitive, capable, efficient, and accessible. It offers compact menus and a streamlined workflow, enabling you to create layout designs quickly and efficiently. Advanced features and functionalities are readily available, empowering designers to deliver high-quality designs efficiently. The informative and interactive panels provide valuable insights, accelerate search and navigation, and effectively manage properties and visibility, ensuring a productive and seamless user experience. Allegro X Layout Editor eliminates the need for modal dialog boxes. Instead, layout toolbars and floating menus reduce distractions and ensure the design space is unblocked and accessible, enhancing productivity and allowing you to focus on your work. Additionally, it includes an integrated 3D viewer that seamlessly switches between 2D and 3D views. This integration enhances visualization capabilities, enabling you to identify and address potential manufacturing issues quickly and efficiently. Allegro X Layout Editor is a powerful, user-friendly, and feature-rich layout environment that facilitates rapid design iterations, reduces time-to-market, and ensures high-quality layouts.

PCIe & DDR IP Solutions for the AI Era and ARM CSS Validation by Eric Li, Senior AE Manager

The rapid advancement of artificial intelligence (AI) is driving a new semiconductor super-cycle, significantly increasing system complexity and performance demands in AI and high-performance computing (HPC). Modern AI “factory” architectures require massive scaling of compute clusters, where efficient data movement becomes a critical bottleneck. As a result, system designs increasingly rely on advanced high-speed interconnects—such as PCIe, UCIe, NVLink, UALink, and Ultra Ethernet—to enable scalable communication across nodes, racks, and data centers. Memory technologies play a central role in addressing these challenges through a heterogeneous hierarchy optimized for bandwidth, power, and cost. High-bandwidth memory (HBM) delivers maximum throughput for AI training, while GDDR supports inference workloads, DDR5-MRDIMM enables scalable system memory, and LPDDR6 provides efficient solutions for AI compute and edge applications. The integration of these technologies reflects a shift toward domain-specific optimization across memory tiers. Cadence addresses these system-level requirements with a full-stack, domain-optimized IP portfolio covering both memory and connectivity subsystems. By delivering silicon-proven controller, PHY, and subsystem solutions across advanced nodes (N3/N2), Cadence enables efficient integration and accelerates time-to-market. Strong adoption among tier 1 customers highlights the importance of comprehensive, validated IP platforms in enabling next-generation AI and HPC systems.

Allegro X AI: Enabling Parallel, AI-Driven PCB Design for Faster and Optimized System Development by Adam Fuchs, Sr Principal Product Engineer

As electronic systems grow in complexity, design tools must evolve to enable higher levels of automation and new ways of working. Allegro X AI provides a pathway for engineers to explore new design approaches by enabling parallel workflows for tasks that have traditionally been sequential.

Allegro X AI combines deterministic algorithms, machine learning, and AI to deliver three key capabilities: automated placement, power and ground plane synthesis, and intelligent routing and trace optimization.

With Allegro X AI Placement, designers can explore multiple board shapes, stackups, and constraint scenarios to rapidly assess design feasibility. Design setups and constraints can be reused across sessions, enabling multiple design scenarios to be evaluated in parallel.

Automated power and ground plane synthesis supports early feasibility analysis, mid-design split-plane generation, and post-routing validation, ensuring robust power delivery and a reliable PDN.

AI-driven routing enables designers to route at any stage of the design while remaining fully constraint-aware, supporting impedance- and timing-controlled high-speed signals along with automated ERC-driven rework.

Combined with integrated analysis technologies, Allegro X AI is enabling a closed-loop, analysis-aware design flow that can continuously refine results and delivers optimized solutions, even for the most complex designs.

Accelerating Hardware Development Through Hierarchical Common Building Blocks by Jason Wong from Celestica

 Modern hardware design faces increasing complexity and shrinking time-to-market windows. This sharing explores the strategic implementation of Common Building Blocks (CBBs) within a hierarchical design framework to streamline the transition from schematic capture to physical PCB layout. By encapsulating complex circuits into discrete functional blocks, this methodology enables a seamless transition into a comprehensive power tree visualization. This provides reviewers and stakeholders with a high-level, intuitive map of the entire power solution, ensuring that voltage rails, current requirements, and sequencing are clearly understood at a glance before diving into the granular layout details.

Electrothermal Co-Simulation for FPGA Package and System-Level Cooling Analysis by Steven Woon from Efinix

 The increasing power density and complexity of modern FPGAs, combined with cost-sensitive product demands, require a unified multi-physics simulation approach bridging chip-level electrothermal behavior with system-level cooling performance. This presentation coupled simulation framework using Cadence Celsius Studio, where the Celsius Thermal Solver (IC package-level analysis) and Celsius EC Solver (full 3D system-level analysis) operate in a complementary workflow for comprehensive FPGA package evaluation. The Celsius Thermal Solver performs detailed electrothermal co-simulation by importing precise power dissipation maps from the IC design flow, calculating Joule heating within bumps, vias and the substrate to generate a high-fidelity junction temperature map revealing localized hot spots. At the same time, a detailed FPGA package-level thermal model can be generated and exported into the Celsius EC system-level model for subsequent simulation, which utilizes Computational Fluid Dynamics to simulate the FPGA within its actual operating environment including the PCB, thermal interface material, heatsink, and enclosure fans evaluating cooling performance under different conditions. This bi-directional workflow ensures chip-level analysis operates under realistic system cooling constraints while enabling simultaneous optimization of electrical performance, thermal integrity, and mechanical reliability, ultimately avoiding over-design and managing product costs.