Grenoble Agenda

Date: Tuesday, November 18

Venue: CoLoft Office

Location: CoLoft - Building E, Arteparc Meylan, 22 chemin du vieux chêne, 38240 Meylan

Parking: Parking spaces are limited. CoLoft encourage visitors to travel via bus or car share where possible.

Salle Décibeldonne (15 parking spaces)

35 Chem. du Vieux Chêne (60 parking spaces)

Bus Stop: C1 Les Béalières

Please view the CoLoft Access and Parking Map here.

Agenda subject to change

Time

Presentation Title

Presenter / Company

08:30 - 09:00

Registration and Welcome Coffee

09:00 - 09:15

Welcome and Introduction

Ran Zhao, Cadence

09:15 - 10:15

10:15 - 11:00

Jasper Update and Roadmap

Improving Productivity with Jasper AI Assistants

Jin Zhang, Cadence

Joerg Mueller, Cadence

11:00 - 11:30

Coffee Break

11:30 - 12:00 

12:00 - 12:30

Large Counter Boundaries Property Checking for BIST Structure

Maximizing PPA Optimization Potential with Jasper SEC

Alessandro Basili, Kandou

Joerg Mueller, Cadence

12:30 - 13:45

Lunch Break

13:45 - 14:15

Achieving Formal Signoff with Bound Signoff Techniques

Vincent Reynolds, Cadence

14:15 - 14:45

Smarter Verification: Leveraging Cadence Formal Apps in NXP DES Digital Flow

Hubert Marcel, NXP Semiconductors

14:45 - 15:15

Taking Formal Verification to a Higher Level with Jasper C Apps

Ran Zhao, Cadence

15:15 - 15:45

Coffee Break

15:45 - 16:15

16:15 - 16:45

Power Intent-Aware CDC Formal Verification for Low-Power SoC Designs

Unlocking the Full Potential of Jasper Visualize: Debug Updates

David Vincenzoni, STMicroelectronics

Vincent Reynolds, Cadence

16:45 - 17:00

17:00 - 18:00

Q&A and Closing Remarks

Happy Hour