Don't miss the following panel sessions, technical presentations and engineering posters!

Monday, July 27

Time
Location

Title

Panelist, Speaker, Authors

10:30am – 11:00am PDT
Exhibitor Forum, Exhibit Floor

LLMs in Production with Chip Teams: Opportunities, Challenges, and Lessons

Kartik Hegde, Cadence 

10:30am – 12:30pm PDT
Meeting Room 104A

Research Panel:: New Minds, New Models: Who Will Drive AI-Led Design Innovation?

Ziyad Hanna, Cadence

10:45am – 11:00am PDT
Seaside Ballroom B

Automated Verification and Performance Analysis for Chiplets

Joshua Lam, Cadence
Batu Bayram, Cadence

1:30pm – 3:00pm PDT
Meeting Room 104A

Research Panel: Who Verifies the Verifier? Trust and Accountability in the Age of Autonomous EDA Agents

Charles Alpert, Cadence

3:00pm – 3:45pm PDT
DAC Pavilion, Exhibit Floor

Cooley's DAC Troublemaker Panel

Paul Cunningham, Cadence 

4:15pm – 4:30pm PDT
Seaside Ballroom A

Efficient IR-Aware Powergrid Optimization

Cadence & Texas Instruments

4:30pm-4:45pm PDT
Seaside Ballroom B

Using Arm Native Acceleration with VLAB Virtual Platforms

Atanas Parashkevov, Cadence
Jeremy Wazny, Cadence 

5:00pm – 6:00pm PDT
DAC Pavilion, Exhibit Floor

Solving Memory Subsystem Verification Challenges for Multi-Instance Designs

Manish Chand, Cadence
Shyam Sharma, Cadence

5:00pm – 6:00pm PDT
DAC Pavilion, Exhibit Floor

Implementing Secure Boot, Attestation, and Secure Storage in Systems in Package

Sylvain Guilley, Cadence
Junie Um, Cadence 

5:00pm – 6:00pm PDT
DAC Pavilion, Exhibit Floor

Risk Analysis for Chiplets and Security Architecture

Sylvain Guilley, Cadence

Tuesday, July 28

Time
Location

Title

Panelist, Speaker, Authors

10:30am – 12:30pm PDT
Meeting Room 104A

Research Panel: Is the EDA Industry Fundamentally Ill-Prepared for True 3D Heterogeneous Integration?

Vinay Patwardhan, Cadence

11:45am – 12:00pm PDT
Seaside Ballroom B

Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio

Cadence & Micron

1:30pm – 3:00pm PDT
Seaside Ballroom A

Engineering Special Session Panel:
Gaps Between MBSE and Semiconductor Design in Aerospace and Defense, Will They Ever Connect?

Matt Graham, Cadence

5:00pm – 6:00pm PDT
DAC Pavilion, Exhibit Floor

Fully Automated On-Chip Inductor Synthesis for High-Frequency VCO with ML-Based Optimization Flow

Cadence & ST Microelectronics

5:00pm – 6:00pm PDT
DAC Pavilion, Exhibit Floor

Multi-Agent Framework for Cross-Boundary Optimization in Hierarchical Floor-Plan-Aware Synthesis

Namra Shastri, Cadence
Prakashkumar Darji, Cadence 

Wednesday, July 29

1:45pm - 2:00pm PDT
Seaside Room 7

A Rule-Aware Layout Conversion Framework for Back-End Physical Design

Cadence & Samsung

2:15pm – 2:30pm PDT
Seaside Room 7

Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework

Loknath Moogi, Cadence
Mohit Gupta, Cadence
Ayush Khare, Cadence

3:00pm – 3:45pm PDT
DAC Pavilion, Exhibit Floor

ECO Strategy for BIG DIE SOC Convergence

Cadence & Samsung

3:00pm – 3:45pm PDT
DAC Pavilion, Exhibit Floor

Mixed-Transistor Design Closure

Cadence & Texas Intruments